Verification Engineer / Lead - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Experience in presilicon verification, preferably processors or north bridges .Skills include test writing, debug, creating and maintaining test environment/checkers/monitors, coverage, test plans .Leadership qualities desired: leading group of 3-5 engineers, mentoring, communicating with remote sites, driving functionality.Hands on requirement a must.Education requirements: MS preferred, BS minimum. Good instutions a plus: IITs, RECs, BITs
SWG-0183063
7 years +
10 years
Bangalore
Will be comunicated post candidate screen select
PSV Validation Engineer - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD: Experience in post silicon validation in System and ATE environments Core Skills: Processor & Chipset validation, characterization, analysis, tools development & silicon debug, hands on experience with lab equipment ( bench, system, ATE), developing and executing test plans.MS preferred, BE minimum. Global footprint desired.
SWG-0183067
6 years +
8 years
Bangalore
Will be comunicated post candidate screen select
OPC/ORC Team Lead - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Technical lead for a team of Engineers in the OPC/ORC areas. Interact with integration and design teams to provide optical proximity corrections on design patterns and improve manufacturability. Support current methods and develop new techniques (including scripts & tools) to address technology issues and keyword challenges. Candidate should have knowledge in reticle enhancement techniques (RET), exposure to design technology co-optimization with exposure to 45nm, 32 nm technologies. Ability to interface with lithography, integration and design teams. Good interpersonal skills with technical depth required, experience with global teams a pig plus.Software skills requirements - Experience with verification tools such as Mentor Calibre SVRF, Cadence Assura, and/or Cadence Virtuoso. C / C++ coding and shell / iTCL / Perl scripting, object oriented programming a plus, Qualifications : candidates must possess a Degree (MS, PhD.) in Computer Science, Electrical Engineering, Physics, or related fields.
SWG-0183060
5 years +
8 years
Bangalore
Will be comunicated post candidate screen select
Signal Integrity Engineers - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Signal integrity, hspice, pwrspice, allegro, electromagnetic modeling, ansoft, sigrity, speed2000, noise, cross-talk, simultaneous switching noise, scattering parameters, BER, eye diagrams, jitter, spectraquest.MS preferred, BE minimum. Global footprint desired
SWG-0183058
5 years +
8 years
Bangalore
Will be comunicated post candidate screen select
Senior Application Architect - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD: Strong in-depth knowledge and hands on Java, J2EE, JSF, Struts,XML, DB2, Web services,WPS, SOA etc.Previous experience in designing enterprise strength, Java server side, commercial grade web services software.Ability to clearly articulate architecture in written form and verbally.Development experience with one or more of WebSphere ,Apache Axis, Axis2, Tomcat, System architecture, J2EE, Java, SOA architect, Websphere, Project management, Rational Suite of Tools, Tivoil, Univ/AIX .Major Field of Study:Software Engineering, Software Architecture ,Web Services Architecture & related technology.Web Services standards and specifications knowledge Java server side development experience.
SWG-0238141
12 years +
16 years
Bangalore
Will be comunicated post candidate screen select
Lead Application Developer - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Strong in-depth knowledge and hands on experience on Java, J2EE, JSF, JDO, Java Script/CSS, Facelets, Portlets, Struts, XML, DB2, Web services, WPS, SOA, Web 2.0 etc. Development experience with one or more Application and web servers : WebSphere, Apache Axis, Axis2, Tomcat web and application servers. Expertise level in using IDE tools like Eclipse, RAD, RSA, Rational Suite of Tools, Tivoil tools, Rational Clear case etc. Major Field of Study: Software Engineering, Agile Practices, Software Development ,Web Services & related technology.
STG-0242449
8 yeras +
12 years
Bangalore
Will be comunicated post candidate screen select
Circuit Design - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Active hands on experience in CMOS Custom VLSI Circuit Design using industry leading tools (CADENCE preferred)Thorough understanding of CMOS technology and devices Familiar with VHDL, schematics entry, circuit simulation (SPICE), custom layout, layout verification methodologies, design for yield and manufacturability, timing analysis, and routing tools.Ability to write CADENCE “SKILL” programming is a plus.Masters Degree, or equivalent .Experience in leading team of circuit designers.
SWG-0183049
10 yeras+
12 years
Bangalore
Will be comunicated post candidate screen select
Integrator Engineers - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Active hands on experience in CMOS VLSI block level/chip integration using industry leading tools (CADENCE preferred).Knowledge of processor concepts, extensive project experience with placement and automatic routing tools, verification methods, design for yield and manufacturability, and timing analysis.Proven record of product deliverables in the area of VLSI products with special emphasis on frequency, area, and power optimization. Knowledge on hierarchical design methods.Script language knowledge (CADENCE SKILL, TCL, Perl, …),Methodology development experience is a plus.Ability to learn and adapt to new tools and methodologies .Masters Degree, or equivalent
SWG-0183045
8 years +
12 years
Bangalore
Will be comunicated post candidate screen select
RLM /Layout - (SPOC - Ancy N Sreenivasan -
ancy.nimsha@in.ibm.com) Brief JD:Active hands on experience in custom VLSI circuit layout using industry leading tools, in particular CADENCE Virtuoso XL . Familiar with custom layout, layout verification methodologies, and design for yield and manufacturability.Familiar with Cadence routing tools such as IC Craftsman is a plus.Ability to write CADENCE “SKILL” programming is a plus Basic understanding of CMOS technology and devices.CMOS Circuit Design knowledge would be advantageous.Work in a Team with Circuit Designer, Integrator and Timing Lead designing next generation microprocessors in cutting edge technology.Responsible for a number of custom layouts which meet timing, power, noise and electromigration requirements.Schematic driven placement and routing of custom macros, run Physical Design tools to generate the layout in Cadence Design Environment (Virtuoso XL).Run all necessary Physical Design (PD) rule checks like DRC, LVS, meth, etc.Optimize Interconnections (Resistivity, Capacitance) for area and delay.Optimize design for Yield and Manufacturability.“Skill” programming for enhanced layout productivity.Deliver all cadence design data according to schedule in required quality.
SWG-0183049
8 years +
12 years
Bangalore
Will be comunicated post candidate screen select
